It is commonly recognized that electrical characteristics of transistors and interconnects are not the same for different chips and even for the same chip at different periods of time or chip locations. Variation of electrical characteristics can be due to variation of process parameters, changing of environmental conditions and even chip age (e.g., Hot Carriers Injections, Negative Bias Temperature Instability, electromigration, and so forth).
The variation of electrical characteristics results in variations of gate timing characteristics. The traditional conservative way to handle these variations is to consider so-called process corners at which the gates have the worst combinations of delays. Then chips are designed so that they can properly function at all process corners assuming that as a result they will function at any other combination of gate delays.
However, with decreasing transistor size and interconnect width, the variation of electrical characteristics is becoming proportionally larger. Therefore, the approach to design for process corners results in too conservative and non-optimal designs because most design efforts and chip resources are spent to make chips function at very low-probability combinations of electrical characteristics.
An alternative approach to designing chips is to consider actual statistical characteristics of process parameter variations and use them to compute statistical characteristics of a designed circuit. For digital circuits, this approach is known as statistical timing analysis. There are several varieties of statistical timing analysis.
One of the most useful for circuit analysis and optimization is parameterized statistical static timing analysis (SSTA). In SSTA, the circuit delay is considered a random variable and the objective of SSTA is to compute its probability distribution. From the cumulative distribution function of the circuit delay, the user is then able to obtain the percentage of fabricated dies, which meets a certain delay requirement, or conversely, the expected performance for a particular yield. In turn, gate or transistor sizing approaches should perform their optimization in a statistical aware manner.
SSTA operates on a timing graph comprised of nodes, which represent points at which signal transitions can occur, and edges that connect incident nodes. Timing values are computed for the timing graph at each node based upon arrival times (ATs), which define the time (or the time distribution) at which a given signal arrives at a timing point, and required arrival times (RATs), which defines the time (or the time distribution) at which the signal is required to get to the timing point, in order to meet the timing requirements. These ATs and RATs are used to compute timing metrics in the form of slacks at nodes (RAT minus AT for late mode and AT minus RAT for early mode). Specifically, a positive slack s at a node implies that the AT at that node may be increased by s without affecting the overall delay of the circuit. Conversely, a negative slack implies that a path is too slow, and the path should be sped up (or the reference signal delayed) if the whole circuit is to work at the desired speed. A negative value for either a late mode slack or an early mode slack indicates a timing constraint violation. One goal of circuit placement is to have no paths with negative slack. Thus, in chip design optimization for a given frequency, typically the overall timing of the chip is closed to a positive slack. Unfortunately, the use of positive slack to close timing on the chip design can be computationally inefficient at times and provide overly pessimistic results.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.